The present invention relates to an improvement in the thermal resistance of a semiconductor device which includes patterned unit cells arranged in a single chip The present invention is particularly effective in reducing the junction temperature of a semiconductor device operating at a high frequency and having high power output.
As the operating frequency of a semiconductor device increases, the size of the device must decrease and the output power producable by the device also decreases. To provide a high power output, therefore, many small elemental devices (for example transistors) are conventionally arranged in parallel on a single chip. Typically, the small elemental devices are connected in parallel and arranged in a group called a unit cell, and several of the unit cells are connected in parallel on a single chip.
The elemental cell, unit cell, and the semiconductor device used in the description hereinafter are defined as follows The elemental cell is an elemental device such as a bipolar transistor or field effect transistor (FET) which is fabricated on a semiconductor substrate. In the high frequency and high power device described herein, elemental cells (usually more than ten) are combined into a unit cell. Further, such unit cells (usually more than ten unit cells) are combined into a single semiconductor device. In a single high frequency and high power transistor device, there are, usually more than one hundred (10.times.10) elemental cells.
For example, in a high frequency and high power bipolar transistor device, emitter regions are fabricated in a base region and these base regions are fabricated in a collector region. A junction between an emitter region and a base region corresponds to one elemental cell, each base region including a group of elemental cells (emitter regions) corresponds to a unit cell, and the collector region including the unit cells (base regions) corresponds to the semiconductor device (the transistor chip or die). Therefore, each base region is a common region for a unit cell, and the collector region is a common region for the semiconductor device (transistor chip). Further details of this structure will be described later with respect to FIGS. 9 and 10. In the following description, a bipolar transistor device will be considered to simplify the description of the present invention.
Elemental cells in a high frequency and high power semiconductor device must have the same pattern or shape. This requirement comes from the design objectives regarding the interconnecting circuit between the unit cells. When the device is operated at a high frequency and the shapes of the unit cells are not the same, it is very difficult to keep the unit cells from becoming unstable and resulting in low efficiency. Furthermore, it is essential that the length of the periphery of the emitter region be as long as possible to obtain a high current output, since the length of the emitter periphery determines the maximum emitter current.
In a high frequency high power device, a large amount of heat is generated in a small area, several mm.sup.2 for example, during high power operation, causing the temperature of the device to increase dramatically. As a result, the junction temperature between the unit cells must be lowered and balanced to produce high power output in the high frequency region and to avoid thermal run away. Generally, a semiconductor device has a tendency to experience thermal run away due to a high junction temperature or an unbalanced junction temperature distribution. That is, the junction current tends to increase as the junction temperature goes up, and the increased current induces further increases in temperature. Once thermal run away occurs, the transistor characteristics degrade and lead to the possibility of catastrophic burn out.
In addition to preventing thermal runaway, lowering the junction temperature and balancing the temperature distribution also lead to improvements in the power output gain, the high frequency operating characteristics, and the life of the transistor chip. In a bipolar transistor, the heat produced in the transistor is primarily generated at the base-collector junction (usually called the base junction). As mentioned above, in a single unit cell, many small emitter regions are fabricated on the base region, and as long as all elemental cells are operated uniformly, heat is generated uniformly over the entire area of the base region. Accordingly, the temperature distribution of the base region is as illustrated in FIG. 1(a). In FIG. 1(a), reference numeral 50 refers to one of the contours of constant temperature for a unit cell 2. As depicted in FIG. 1(a), the temperature is highest at the center of the unit cell.
Thermal run away tends to occur in the center of the device, because the temperature at the center is usually the highest. This tendency is more noticeable when the area of the unit cell is large. If a high power semiconductor device has a structure consisting of a single unit cell having a large area, the amount of the heat generated by the device would be so high that the device would not be able to keep the thermal and electrical imbalance from resulting in thermal run away. Consequently, high power and high frequency semiconductor devices consist of uniformly distributed unit cells (base regions) 2, each covering a relatively small area.
A chip having high frequency and high power transistors is usually mounted on a heat sink. Most of the heat generated at the base junction flows from the base region of the unit cell 2. As a result, heat flow has flow-vector components both perpendicular and parallel to the base junction. The theoretical calculation of the heat flow and the temperature distribution can be made by solving Poission's equation. This is described in, for example: D. P. Kennedy "Spreading Resistance in Cylindrical Semiconductors" J. Appl. Phys. pp. 1490-1496, (1960). However, the calculation for an actual semiconductor device is very complicated and requires extended computation time on a high speed, large memory computer. As a consequence, a simple approximation using the concept of thermal spreading angle has been generally applied as a substitute for the complicated calculation. This approximation is also based on the solution of the Poission's equation, so that most of the heat flow is within an area included in the spreading angle determined by the boundary conditions of the device. Using the concept of the spreading angle, the heat flow of semiconductor devices will be explained hereinafter.
FIGS. 2, 3 and 4 are cross-sectional views of a semiconductor device illustrating heat flow in a substrate. A collector region (substrate) 1 abuts a base region (unit cell) 2 at a base junction 21. The heat generated at the base junction 21 flows to a heat sink 9 through the collector region 1 in a diverging pattern so that the heat flux (shaded area) spreads, creating a flux edge 3 at the plane of the heat sink 9. FIG. 2 illustrates the heat flow from the base junction 21 to the heat sink 9 without considering any heat flux influences from other unit cells and thereby corresponds to the temperature distribution on the chip surface illustrated in FIG. 1(a). As illustrated in FIG. 2, the heat flow through the collector region 1 diverges as indicated by the shaded region.
When a plurality of base regions 2 are arranged on the same collector region 1, heat interaction occurs between them. This interaction is illustrated in FIG. 3 in which the heat flow from each base region 2 interacts with that from other base regions 2 in a heat overlap zone 4. The larger the area of the overlap zone 4, the greater the thermal resistance of the collector region 1. This increase in thermal resistance raises the temperature of the unit cell 2 such that the contours of constant temperature 50 lose their symmetry as depicted in FIG. 1(b), resulting in unbalanced operation of the unit cells 2. In the prior art, based on the concept of the heat spreading angle, the base regions 2 are arranged to avoid large heat overlap zones 4, but at the same time, arranged as close as possible to each other to increase the packing density of the device and decrease the inductance and parasitic capacitance of the interconnecting circuit on the chip surface and the wirings, for high frequency operation.
The spreading angle (.theta.) of the heat flow illustrated in FIG. 2 can be obtained experimentally by measuring the thermal resistance of a single unit cell 2 and generally has a value between 40 degrees and 60 degrees. The spreading angle .theta. is often applied to pattern pitch design of unit cells 2 in power transistors.
Because of prior art heat dissipation limitations, no prior art single chip bipolar transistor is rated for a continuous wave (C. W.) output power of more than 50 W at 900 MHz. This value has been viewed as a practical limit for high frequency and high power semiconductor single chip devices.